Constant ΔTj Power Cycling Strategy in DC Mode for Top-Metal and Bond-Wire Contacts Degradation Investigations

The study of the impact of junction temperature swings (ΔTj) on degradation mechanisms during power cycling tests (PCTs) requires both a control of the applied thermal stress and a separation of degradation modes. The first requirement can be obtained by using a “constant ΔTj” power cycling strategy that allows to minimize the cross interactions between the influencing factors. The second one is made by using a dedicated power module well suited for targeting only the chips top-side degradations (metallization and bond-wire contacts). In this paper, a constant ΔTj strategy by gate voltage regulation is performed for PCTs in the dc mode. The tested modules are ideally designed for top-metal and bond-wire contacts degradation investigations. From aging indicator on the collector-emitter voltage (VCE), the results clearly show that three regimes of degradation occur systematically at the insulated gate bipolar transistor (IGBT) chips top side, whatever the stress conditions. Moreover, comparative results in “constant ΔTj” and conventional “constant ΔI” PCT strategies have shown that the feedback between stresses and damages encountered in the second strategy is more important for low ΔTj values than for high ΔTj values. In addition, results show that in case of high stresses, the “constant ΔTj” strategy with VGE regulation gives values close to a “constant ΔI” strategy but that the extrapolation toward low values of ΔTj can be questionable for the “constant ΔTj” strategy.