Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion

Stochastic computing (SC) is an unconventional computing technique using digital circuits. It performs arithmetic computation on stochastic bit streams (SBSs), which encode real values through the ratios of ones in the streams. Despite its advantages such as simple arithmetic units and strong error tolerance, SC faces two big challenges: 1) long computation latency and 2) large hardware overhead to generate independent SBSs. A recent work proposes to insert D flip-flops (DFFs) into the stochastic circuit to reduce the overhead to generate SBSs. In this paper, observing that DFFs can also be exploited to reduce circuit delay, we propose a novel method to insert DFFs into a stochastic circuit to simultaneously reduce the computation latency of the circuit and the overhead of generating SBSs, thus addressing both challenges at the same time. Experimental results showed that compared to the state-of-the-art method in optimizing stochastic circuits with DFF insertion, our method can reduce the computation latency by 14.3% and the number of DFFs by 48.1%.