Pairing ILVs for testing monolithic 3D integrated circuits

Monolithic three-dimensional (M3D) integration is a powerful technology for implementing 3D integrated circuit (IC). Designs using M3D structure have CMOS process in the bottom layer, and silicon-on-insulator (SOI) on top layer. It is necessary to test the bottom layer of M3D IC for identifying faults due to defect in manufacturing process. An e-fuse based bypass structure is considered for connecting the inter-layer vias (ILVs). In this paper, we propose a heuristic approach to maximize the e-fuse connection between pair of ILVs and minimize the wire length between paired ILVs. The independent ILVs, those are not paired, are minimized to a lowest possible value. Results are obtained for different ITC'02 test benchmark circuits.