Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure

This paper presents a novel delay model for Inverter followed by Transmission Gate (Inv-Tx) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitances while treating the Inv-Tx structure as a single entity. The model is derived for an unexplored scenario when a static signal is present at the input of Inverter and signal transition happens at the input of Tx gate of the Inv-Tx structure. Since we consider Inv-Tx structure as a single entity, the series stack effect is taken into account, thereby making the model more accurate. We also demonstrate the transformation of our delay model into the Logical Effort model. The derived model is verified for wide range of transistor sizes, signal transition times, and load capacitances. The proposed model shows good agreement with HSPICE simulation results. The maximum (average) error in the estimated delay compared to HSPICE simulations is only 4% (2%). The proposed model is also effective in accounting for process variability. The proposed model is employed for statistical analysis of 256×1 MUX structure. We observe that in the presence of variability, the proposed model predicts mean and standard deviation of the delay with a maximum error of only 3% and 4% respectively. Therefore, the presented model can also be used for statistical analysis to save simulation time significantly.