Quantifying the Interaction Between Structural Properties of Software and Hardware in the ARM Big.LITTLE Architecture

Heterogeneous architectures offer the opportunity to achieve high performance and energy efficiency by selecting appropriate cores for execution of ever changing software applications. Appropriate core selection depends on the interaction between the structural properties of the software and the hardware that influences performance of the software. We propose a model for efficient core selection when executing software on ARM's big.LITTLE heterogeneous architecture. It features a metric based on the correlation between the performance and the number of last level data cache (LLC) misses on a big and a LITTLE core. Additionally our model defines a soft threshold in terms of the number of LLC misses that determines efficient core selection. We verify the model on both a stress benchmark (stress-ng) and a performance and energy demanding application (HEVC decoding) using XMEM and Linux perf dynamic tools.