A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM

A double sensing with selective bitline voltage regulation (DS-SBVR) scheme is proposed to improve the throughput of ultralow-voltage static random access memory (SRAM). It senses the bitline voltage swing twice and compares two samples for confirmation. The bitline voltage is dynamically regulated by charge sharing between two sensing steps. Different from other timing speculative SRAMs, its error flag is generated much earlier; therefore, it achieves a higher reading throughput. Meanwhile, a digitized timing scheme is proposed to generate configurable timing pulses for the DS-SBVR. Compared with other timing techniques, it has a better ability to process, voltage, temperature (PVT) tracking and variance suppression. For fair comparison of performance/power/area, three different columnbased timing speculative designs are implemented in the same technology. A 28-nm test chip including 40 SRAM macros (128 × 32) is fabricated to demonstrate the scheme. Compared with the conventional design, measurements show that DS-SBVR achieves 1.45× throughput gain at 0.6-V SS corner. The figure of merit (FOM) is introduced for power, performance, and area (PPA) gain comparison. Compared with the conventional design, the FOMs of PPA gain are 1.54 and 2.33 in 128-row and 512-row memories, respectively. Compared with other timing speculative SRAMs, it achieves 1.83×-2.24× improvement.