Defect learning methodology applied to microbump process at 20μm pitch and below

Over the last years, 3D TSV technology and 3D stacking have moved into the preproduction and yield ramp phase. The characterization of many of the different critical modules within the 3D stacking integration flows is becoming more and more crucial. Microbump dimensions are being scaled down to the pitch of 20μm and below. This scaling is required in order to achieve higher interconnect densities. For yielding vertical interconnects in die-to-die and die-to-wafer stacking, highly accurate and repeatable measurements and inspections of microbumps are an absolute must for this technology to become a viable industrial option. Microbump process control is usually a hybrid approach of inspecting the full wafer including all microbumps and specific microbump metrology. This eventually enables correct die classification and selection of known good die for further integration in 3D packages. Prior to being able to classify and disposition die based on microbump integrity, yield critical defect types need to be identified, defect mechanisms need to be understood and dimensional features impacting further processing need to be characterized. This paper addresses these requirements and elaborates on the applied defect learning methodology based on a significant amount of microbump process monitor wafers. Yield loss by every defect type was quantified and root causes for these yield critical defect types were discovered. From this analysis, further process improvement projects can be initiated, parameters for statistical process control derived and known good die for yielding die-to-die and die-to-wafer stacking can be identified and separated from failing die.