An evaluation framework for security algorithms performance realization on FPGA

Security algorithms play a major role in most of the applications which include electronic gadgets, mobile banking, e-commerce, military, digital image processing, satellite & wireless communications, etc. The realization of the cryptography algorithm on FPGA is an open research problem to meet its benchmark to provide security essentials of confidentiality, integrity, and authentication in fast and accurate ways on future compact devices. This paper proposes an evaluation framework for realizing FPGA for cryptographic algorithms including DES, LED, TDES, AES-128, AES-192, and AES-256 with a symmetric key for both encipher and decipher. The framework is evaluated for its performance metrics of the area, operating frequency and power by hardware prototype architecture for these algorithms on Artix-7 FPGA device. The comparative analysis is presented for these metrics to get insights of its effectiveness on FPGA.