RideNN: A New Rider Optimization Algorithm-Based Neural Network for Fault Diagnosis in Analog Circuits

Fault diagnosis in electronic circuits is an emerging area of research, where fully automated diagnosis systems are being developed for the investigation of the circuits. Developing test methods for the diagnosis of faults in analog circuits is still a complex task. Consequently, a technique for the fault diagnosis in analog circuits is designed by proposing a new optimization algorithm, named, rider optimization algorithm (ROA). The development of ROA is based on a group of riders, racing toward a target location. Moreover, a classifier, termed RideNN, is developed by including the proposed algorithm as the training algorithm for the neural network (NN). RideNN, along with the orthogonal transformation and Bhattacharyya coefficient, is applied for the fault diagnosis of analog circuits. The proposed technique is experimented using three basic circuits, such as triangular wave generator (TWG), low noise bipolar transistor amplifier (BTA), and differentiator (DIF) and an application circuit, solar power converter (SPC). The performance is evaluated using two evaluation metrics, namely, accuracy (ACC) and false alarm ratio (FAR). The analysis results show that the proposed technique attains an ACC of 99.9% in TWG, 99.9% in BTA, 99% in DIF, and 95% in SPC without noise.

I. Introduction

Due to the wide application of analog circuits in military, automatic control, household appliances, communications, and so on, an enhanced technology associated with the fault diagnosis of analog circuit is extremely essential [1]. The immense applications of analog circuits have caused fault diagnosis to become an active area of research. Henceforth, different methods are being developed. However, there are various issues in the fault diagnosis of analog circuits, which have been addressed by the researchers at the chip level and the system board level [2], [3]. Though various automatic fault-testing strategies are being designed for diagnosing the faults in the analog circuits, the development of effective techniques is still an open research area [1]. One main reason is that the process of developing the test strategies for the analog circuit diagnosis heavily relies on the engineer’s experience and intuition. Fault identification in any analog circuit is necessary to ensure its reliability, since the process of fault diagnosis is complicated than in the digital circuits due to nonlinear effects, component tolerance, worst fault models, etc [4]. Moreover, the usage of a larger number of response parameters introduces difficulty in testing, in addition to its cost [2].