Minimizing electro-mechanical shifts in IC applications

With the ever increasing functionality of modern electronics many applications have emerged using high-performance-mixed-signal ICs. Many of these ICs require control of device parameters in the sub-one-percent range. To reach such precision, trimming on wafer level is commonly employed. Trimming is needed due to slight dimensional differences caused by the front-end process variation and small differences in mechanical stress between the products. The piezo-electric effect, responsible for causing changes in electrical parameters due to mechanical stress has been studied extensively. [1-4] In this paper we study the effects of the time-temperature behavior exhibited by organic materials at the die-package level on the electrical performance of typical devices used in IC design such as pMOS, nMOS and vertical PNP bipolar junction transistors (vPNP). With some applications, minimizing the coupling between the materials that exhibit time-temperature dependent behavior and the sensitive circuitry will ensure that a properly-trimmed circuit will behave predictably during its lifetime. We explore potential solutions based on integrated die-package stress buffers. Buffers used to decouple the IC circuitry from the surrounding packaging materials are investigated by simulation and experimentation. A response surface model is used to find a limited set of geometrical configurations for sample builds via virtual prototyping. Using thermo-mechanical simulations, we were able to limit the number of relevant design parameters and predict the sensitivity of the circuit for each of them.