Fabrication and Analysis of Vertical Thin Poly-Si Channel Transfer Gate Pixels for a 3-D CMOS Image Sensor

This paper reports the process integration and fabrication characteristics of a vertical thin poly-Si channel (VTPC) transfer gate (TG) pixel, which is one of the candidates for future 3-D CMOS image sensor (CIS) applications. The proposed process integration can effectively suppress grain boundary formation at the interface between the photodiode and the poly-Si channel by solid phase epitaxial growth (SPEG) mechanism. Furthermore, dopant diffusion characteristics for source-drain junction formation in polySi substrates are investigated using secondary ion mass spectroscopy (SIMS) depth profiles under various process conditions. In addition, combining SIMS results with Id-Vg curve and scanning spreading resistance microscopy measurements, we explained the discrepancy in diffusion characteristics between the bulk and the thin-film poly-Si. Finally, by using optimized SPEG conditions and adopting the proposed VTPC-TG pixel structures in a commercial 5-Mpixel CIS image sensor product, we successfully-verified the improvement in image quality.