Technology mediated tutorial on RISC-V CPU core implementation and sign-off using revolutionary EDA management system (EMS) — VSDFLOW

VSDFLOW (VLSI System Design Flow) is a `plug and play (PnP)' EDA management system, built for chip designers to implement their ideas and convert to GDSII. `plug and play (PnP)' refers to switching between any EDA tools, for e.g. user can plug Cadence Genus for synthesis, Synopsys ICC for PNR and Tempus for sign-off STA. The output report will provide a QOR of entire design, which forms the starting point for design analysis. At this moment, it has been tested on medium sized designs like picorv32 - a RISC-V CPU core that implements RV32I instruction set, using 180nm PDK's from OSU and 45nm PDK's from Nangate. `vsdflow' was also tested on designs like ARM Cortex-M0, which is available as an evaluation IP on ARM website.