A study of 28NM LDMOS linear drain current degradation induced by hot carrier injection

LDMOS (Laterally Diffused Metal Oxide Semiconductor) applications get extensively in high voltage and smart power management. However, high operational drain voltage makes LDMOS devices highly vulnerable to the damage caused by HCI (hot-carrier injection). In this paper, shallow trench isolation (STI) based LDMOS linear drain current (Idlin) degradation induced by HCI (hot carrier injection) was systematically studied with the various layout parameters of NLDMOS (n-channel LDMOS) and well implant condition using 28nm Poly/SiON logic process, extensive TCAD (Technology Computer Aided Design) simulations and experiments revealed that layout, OPC (optical proximity correction), well implant optimization can greatly improve NLDMOS linear drain current degradation induced by HCI. The physical mechanism behinds the results should be that the impact ionization region has been driven further away from the STI edge and Si/SiO2 interface with a reduction in magnitude, which can reduce Idlin shift induced by HCI stress and make sure NLDMOS HCI pass industry general criteria of Idlin shift.