Economic Analysis of Transfer Printed III–V Virtual Substrates

We propose a novel methodology for III-V substrate cost reduction that does not rely on chemical-mechanical polishing (CMP) or low-throughput release layer etching. The details of this process are provided, and results of an economic model for GaAs and InP virtual substrates dictate 20x and 34x reductions to substrate cost, respectively. The impact of modeled assumptions are quantified in order to better understand the potential range of end-goal virtual substrate cost.