FFT implementation and optimization on FPGA

Nowadays, the development of the Fast Fourier Transform (FFT) remains of a great importance due to its substantial role in the field of signal processing and imagery. This latter still attracts the attention of several researchers around the globe. In this paper, an optimized design of the FFT using the radix-2 algorithm, 32 point is proposed. The developed architecture was implemented using an FPGA regarding its flexibility as well as its parallelism and its computational speed. Though, the material resources of the FPGA are limited, particularly the integrated DSP blocks, a new calculation approach was introduced during the VHDL description with the aim to reduce the necessary number of multiplication operation. The experimental validation of the adopted architecture was realized using a Virtex 6, where the numerical synthesis and the post and route described in VHDL was realized using ISE Design Suite 14.7.