SEE Error-Rate Evaluation of an Application Implemented in COTS Multicore/Many-Core Processors

This paper evaluates the error rate of a memory-bound application implemented in different commercial-off-the-shelf multicore and many-core processors. To achieve this goal, two quantitative experiments are performed: fault-injection campaigns and radiation ground testing. In addition, this paper proposes an approach for predicting the application error rate by combining the results issued from both types of experiments. The usefulness of the approach is illustrated by three case studies implemented in processors having different manufacturing technologies and architectures: 45-nm silicon-on-insulator (SOI) free-scale P2041 quad-core processor, 65-nm CMOS Adapteva Epiphany multicore processor, and 28-nm CMOS Kalray multipurpose processing array-256 many-core processor. The reliability of the processors for avionics is obtained from their experimental error rates extrapolated to avionic altitudes. Reliability curves are plotted for observing the prediction accuracy. A comparison of the failure in time of the selected processors shows that the greater single-event effect vulnerability of CMOS technology compared with the SOI one can be compensated with the implementation of effective error detection and correction. These protection mechanisms allow the use of CMOS devices having huge memory capacity in applications operating in severe radiation environments.