Shared‐Bus and Shared‐Memory‐Based Switch/Router Architectures | part of Switch/Router Architectures: Shared-Bus and Shared-Memory Based Systems | Wiley-IEEE Press books | IEEE Xplore

Shared‐Bus and Shared‐Memory‐Based Switch/Router Architectures


Chapter Abstract:

The first generation of router and switch/router designs has relied upon centralized processing and shared memory for forwarding and buffering packets, respectively. Thes...Show More

Chapter Abstract:

The first generation of router and switch/router designs has relied upon centralized processing and shared memory for forwarding and buffering packets, respectively. These designs have traditionally been based on a shared bus switch fabric. This chapter provides examples of switch/router architectures. Improvement in the performance of the shared‐bus based architectures can be obtained by distributing the packet forwarding operations to other processors or to the line cards. Some architectures distribute forwarding engines and flow/route caches, in addition to receive and transmit buffers, to the line cards to reduce the load on the system bus and also improve overall system performance. One approach widely used to overcome the performance limitations of bus‐based architectures is to use architectures that employ high‐speed shared memory switch fabrics and distributed forwarding engines. A key advantage of this architecture is that, the shared‐memory can be used to temporarily store packets in large buffer memories to absorb the traffic bursts in networks.
Page(s): 43 - 60
Copyright Year: 2018
Edition: 1
ISBN Information: