A high linearity wideband receiver with large dynamic range in 0.18um CMOS

A high linear, low power wideband CMOS receiver for digital set-top boxes or satellite low cost terminals is presented. It is implemented based on Zero-IF structure for a fully integrated chip and Supports different reconfigurable symbol rates. It is made up of LNA, down frequency conversion circuits, orthogonal analog baseband, fractional PLL, supply management, digital interface and necessary auxiliary circuits. Fabricated in TSMC 0.18um 1P6M MM/RF CMOS process and packaged in QFN40, the receiver performance is measured showed as: the input 1dB gain compression point is above 0dBm in 0.9-2.2GHz, noise figure is below 10dB, dynamic range is larger than 80dB, bandwidth of adjustable LPF is between 4MHz and 40MHz, and I/Q paths mismatch are smaller than 0.1dB for amplitude and 0.05 degree for phase with calibration. The area of the whole transmitter is 3.9mm × 3mm. The chips have passed relative system test verification, preparing for pilot.