Low power ASIC implementation of signed and unsigned wallace-tree with vedic multiplier using compressors

Multiplier is an important block in most of the digital signal processor (DSP) and high performance systems. The performance of such systems can be improved by implementing high speed multiplier. In this research work new modified compressor based multiplier architecture is introduced. This structure uses the 3-2, 4-2, 5-2 and 7-2 compressors architecture which has less area compare to normal adders. The comparison was made on synthesis results of all other adder, comparison shows that the new introduced adders consume less area and power. In addition to that it uses Vedic multiplier and unsigned Baugh-wooley Wallace tree multiplier to increase the performance of multiplier with less area and power. The ASIC Implementation can be done using Cadence 45nm CMOS technology. Further optimization can be done using other physical design optimization algorithm.