A 350-mV, under-200-ppm allan deviation floor gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS

This paper presents a gate-leakage-based timer using an amplifier-less replica-bias switching technique that can realize stable and low-voltage operation with logic circuits based architecture. To generate stable oscillation frequency in low power operation, the topology that discharges the pre-charged capacitor via a gate leaking MOS capacitor with low-leakage switch is employed. The proposed amplifier-less replica-bias switching technique enables the low-voltage operation of the timer by tracking the discharging node of the capacitor and minimizing the leakages through the switch without analog circuits. The native NMOS header is implemented to reduce supply sensitivity of the timer. The test chip fabricated in 55-nm deeply depleted channel (DDC) CMOS technology achieves an energy efficiency of 25 pJ/cycle at a supply voltage of 350 mV with a body bias in a 0.0022 mm
²
area, and 200-ppm Allan deviation floor.