A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65 nm CMOS. A true arbitrary non-linearity calibration scheme is specifically proposed for synthesizable DTC, together with an extensive digital calibration of the PLL. The RMS jitter of 1.2 ps and 0.3 ps is achieved at 1 GHz output for fractional-N and integer-N operation, respectively. The power consumption is 2.5 mW and 2.2 mW, corresponding to an FoM of −234.4 dB and −246.7 dB.