High Retention With ${n}$ -Oxide- ${p}$ Junctionless Architecture for 1T DRAM

This paper reports on the potential benefits of a vertically stacked n- and p-type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention time (RT) of capacitorless dynamic random access memory (1T-DRAM), with a significant improvement (~×10
³
) compared with a conventional JL transistor with a doping (Nd) of 10
¹⁹
cm
^-3
. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top n-type JL transistor) and storage region (bottom p-type JL), while maintaining an electrostatic coupling between them. The charge stored in the p-type JL determines RT, and also impacts the read currents, and thus, influences the sense margin of DRAM. Stacked JL (SJL) 1T-DRAM achieves a maximum RT of ~2.5 s for Nd = 5 × 10
¹⁸
cm
^-3
and ~1 s for 10
¹⁹
cm
^-3
with a gate length (L
_g
) of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The enhanced DRAM metrics (better scalability and high RT) are attributed to optimal architecture due to the vertical stacking of n- and p-type regions.