A 6.25GHz, 2.7μw at 0.5V, double-tail comparator using charge-steering approach

The ultra-low power and high-speed dynamic regenerative comparator is required for several ultra-low power and high-speed data converters. A proposed dynamic double-tail comparator has been providing using charge steering approach. This approach consumes less power than current steering approach and also very promising for high-speed semi-analog circuit. The proposed and conventional double-tail dynamic (DTD) comparator have been designed and simulated using 65nm TSMC CMOS technology. The proposed circuit consumed 2.7μW and achieved 6.25GHz frequency at 0.5V power supply. The proposed design provides a significant enhance for the power and speed over conventional design.