A design of a new resistor string DAC for phones applications in 130nm technology

This paper presents a design of a new resistor string digital-to-analog converter (DAC) in 130-nm CMOS technology for phones applications. The proposed DAC was designed with a resistor string architecture for high frequency, high speed, high accuracy and low glitches, optimized deglitch circuit is adopted for the selection of resistor string. The layout occupies a small active area of 32.80um × 46.90um in CMOS 130nm, the power consumption is only 361.574 uW, the measured integral nonlinearity (INL) and the measured differential nonlinearity (DNL) respectively are ±0.00026LSB and ± 0.00034LSB.