Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process

Three different latch structures are fabricated in a 65 nm FDSOI process. We evaluate soft-error tolerance of latches by device simulations and a particle, neutron, heavy-ion irradiation tests in order to identify which transistor type is dominant to cause soft errors. The latch structure including an inverter with stacked NMOS and unstacked PMOS transistors has enough tolerance against soft errors by up to heavy ions with 40 MeV-cm
²
/mg. It suggests that soft error rates are dominant on NMOS transistors not only in terrestrial regions but also in outer space.