Degradation of vertical GaN FETs under gate and drain stress

The aim of this paper is to report the first experimental analysis of the degradation of GaN-based vertical transistors (VFETs) subjected to gate- and drain step-stress. Based on combined pulsed measurements and step stress tests we demonstrate the following original results: (i) the analyzed devices (optimized for 200 V operation) do not show significant current collapse up to V
_D
= 200 V; (ii) under positive gate bias (V
_Gstress
> 0 V) the devices show a positive threshold voltage shift, which is ascribed to the injection of electrons into the gate dielectric, and an increase in the sub-threshold slope (SS, mV/dec), which is ascribed to the detrapping of electrons from the gate-insulator to the gate metal. Under the same conditions of stress we observe an initial decrease in the on-resistance, which is ascribed to a reduced scattering at the dielectric/GaN interface. 2D simulations were carried out to support the interpretation of the experimental data.