On the ESD behavior of a-Si:H based thin film transistors: Physical insights, design and technological implications

In this work, we present detailed physical and technological insights into the ESD behavior of a-Si:H TFTs. Pre-Breakdown mechanism is investigated using Electron microscopy, Raman spectroscopy and on-the-fly I-V/ C-V measurements in between TLP stress. Competing mechanisms of device failure and effect of various performance parameters on failure threshold are investigated. Effect of channel dimensions on failure mechanism is thoroughly explored. For the first time, ESD behavior of a-Si:H display technology based Gated diodes and Resistors is reported. Detailed investigation on Drain Underlap devices and their possible usage as I/O protection device in a-Si:H technology is discussed.