Stochastic Propagation Delay Through a CMOS Inverter as a Consequence of Stochastic Power Supply Voltage—Part I: Model Formulation

We derive analytically expressions for the probability distribution of the propagation delay time of logic signals through a CMOS inverter when the inverter power supply voltage V
_dd
(more precisely, gate voltage V
_GS
) is itself probabilistic for some reason (e.g., system noise or a random external electromagnetic disturbance). Since the propagation delay time is a function of the value of V
_dd
, then some values of V
_dd
may produce values of the inverter propagation delay time that cause the circuit in which the inverter resides to malfunction (e.g., by resulting in an inverter delay time value not conforming with the delay time margins for that circuit). Based upon the derived inverter propagation delay time probability distribution, we then derive a probability for the malfunction of a circuit containing a single inverter subject to such a stochastic V
_dd
. In this paper, we present no discussion of the application of our formalism to example probability density functions for V
_dd
; we rectify this situation by presenting three detailed such examples in a companion paper in this journal.