Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing

Time-based circuit design is becoming increasingly popular due to its ability to overcome the challenges imposed by technology scaling such as supply voltage reduction and finite output impedance. In this paper, we present synchronous circuit techniques for the design of discrete-time time-mode filters based on the operational simulation of LC ladders or a cascade of bilinear/biquads. Operating with a 130-kHz clock frequency, two low-pass filter prototypes have been constructed in a 1.2-V, 130-nm IBM CMOS process. The measurements confirm the validity of the proposed approach.