Repeater insertion method and its application to a 300 MHz 128-bit 2-way superscalar microprocessor

Interconnect delay is dominant in today's high speed VLSI circuits and there have been various studies on ways to resolve it. A repeater insertion tool "RePertory" has been developed to solve the interconnect timing problem on a 300 MHz 128-bit 2-way superscalar microprocessor. Because of its practical simple algorithm, the location of over 5700 repeaters distributed over 5 modules is calculated in 26 minutes on 5 UltraSPARC-II 360 MHz in parallel. This paper describes the goals of RePertory for this project, the timing improvement flow with RePertory, the results and analysis of this repeater insertion method.