An Energy-Efficient 11-bit 10-MS/s SAR ADC with Monotonie Switching Split Capacitor Array

In this paper, a 11-bit 10MS/s asynchronous differential SAR ADC is presented. A monotonic switching procedure is used with a split capacitor structure to reduce the area and energy consumption. A digital calibration method is proposed to minimize the effect due to capacitor mismatch and the bridge parasitic capacitor. The SAR ADC is implemented with a 0.18um CMOS technology. At a 1.8-V supply and 10 MS/s, the ADC achieves an SNDR of 65.2 dB and consumes 0.62 mW, resulting in a figure of merit (FOM) of 42.8 fJ/conversion-step.