A Hardware Accelerator for Anisotropic Diffusion Filtering in FPGA

Digital image processing is a fundamental part of computer vision systems and uses filtering techniques to improve image quality and highlight details of interest. The Anisotropic Diffusion Filter is widely used for smoothing and noise reduction, preserving region edges. This paper presents the implementation of a hardware accelerator that executes an Anisotropic Diffusion Filter algorithm in an FPGA, focusing on accelerating the execution of an embedded software solution. Results demonstrate that the co-processor allows reducing the time for processing the Anisotropic Diffusion Filter while obtaining the same quality of a 32-bit RISC-based implementation. Furthermore, the solution is scalable and allows to improve performance by exploiting spatial parallelism.