On-Fly Offset-Correction Method for High-Speed Comparators using All-Digital Phase Measurement

This paper presents a low-cost technique to reduce offset voltage of a dynamic comparator. The proposed method is based on output-data phase measuring through a digital implementation without impacting offset accuracy. The technique requires less than 500ns to achieve convergence and calibration without needing to break the signal path associated to the comparator during regular link operation. An on-a-chip emulated channel and front-end with a sampling circuit has been implemented in 130nm CMOS along with a chip-scope capability to measure eye diagrams at the input of the sampler. Although the concept has been implemented in a low speed interface considering available technology, the implementation shows potential to port the proposed offset correction scheme to a state-of-the art process node applied to links featuring data rates with tens of Gb/s.