A 10-bit 200-kS/s 1.76-μW SAR ADC with Hybrid CAP-MOS DAC for Energy-Limited Applications

This paper presents a low-power and area efficient 10-bit SAR ADC with hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC, which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of 8 MOS transistors to control one unit capacitor, the 3-bit LSB MOS DAC is realized by a MOS string with 4 native MOS transistors to control 2 unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared with a Vcm-based 10-bit pure CDAC. Under a 200-kS/s conversion rate, the prototype 10-bit SAR ADC is implemented in a 0.18-μm CMOS technology, showing an SNDR/ SFDR of 56.91 dB/68.56 dB at 99-kHz input under a 0.6-V power-supply, while consuming 1.76 μW at 200 kS/s for a FoM of 15.38 fJ/step. The peak DNL and INL are +0.27/-0.21 LSB and +0.43/-0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm
²
.