Design of a 6th-order Continuous-time Bandpass Delta-Sigma Modulator with 250 MHz IF, 25 MHz Bandwidth, and over 75 dB SNDR

This paper presents the design of a 6^th-order continuous-time bandpass delta-sigma modulator that achieves in simulation over 75 dB SNDR across 25-MHz bandwidth with a center frequency at 250 MHz. On the architectural level, the SNR-limiting factor is identified and analyzed. A combined feedback-and-feedforward topology is employed that both reduces the number of feedback DACs and effectively suppresses the thermal noise from the 1^st resonator by over 7 dB. On the transistor level, this paper focuses the discussion on the loop filter. The effect of op amp non-ideality is studied. A 5^th-order multistage feedforward op amp is proposed to enhance loop filter linearity. Simulated in a 65 nm CMOS process, this design consumes 156 mW from a 1.2 V supply at a clock frequency of 1 GHz, predicting a state-of-the-art Walden figure-of-merit (FoM) of 0.597 pJ/step.