Novel Time-Based Sensing Scheme for STT-MRAMs

This paper proposes a novel STT-MRAM sensing scheme based on time-based sensing (TBS). The TBS scheme converts the bitline voltage into time, then sensing is performed in the time domain rather than in conventional voltage or current domain. Monte Carlo simulations in 65nm show that the proposed TBS improves the read bit error rate (BER) by two-three orders of magnitude, compared to conventional sensing circuit. This is achieved at the cost of less than 1% area penalty and 13-14% performance degradation, and an insignificant (2%) energy penalty when designed at iso-area (minimum delay). As further advantage, TBS requires no analog reference generation and distribution by leveraging gate delay as an implicit timing reference.