Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits

This paper presents a fast timing analysis methodology that can be applied to full-custom digital circuits. Given a transistor-level circuit netlist, we build a timing graph that consists of gates and wires. Each gate is modeled as a set of equivalent RC networks representing a specific input pattern while taking into account of stacked transistor effect and Miller effect. Wires are also modeled into RC trees using a Rectilinear Steiner minimal tree. An improved RC delay model that takes input transition time into account is used for computing the propagation delays of the RC networks, which is also proposed in this paper. Gates and wires are then modeled into a hardware description language (HDL) so that the timing analysis is performed using an off-the-shelf function simulator. Experimental results on a few test circuits indicate that up to 1800× faster timing analysis can be realized compared to SPICE; the average error of the proposed delay model is 11.2%.