Carry look ahead adder design using CMOS output wired logic based majority gate

Carry look ahead adder has been designed in the paper using the concept of majority gate and output wired logic. The circuit is designed for two bits and the power delay product is calculated for the carry look ahead adder. The transistor count for the proposed design of carry look ahead adder is less than the conventional design. The major advantage of the design is its fast computation and less power consumption and delay. The design has been verified using tanner tool.