Fault masking ratio analysis of majority voters topologies

The continued transistor scaling is resulting in circuits even more sensitive to faults, causing a several impact on circuit reliability. Hardware redundancy is constantly applied to mitigate this problem. One of the most adopted technique is the Triple Modular Redundancy (TMR). Therefore, the voter is the weak part of the TMR system and for this reason, many topologies have been proposed in the literature. This work investigates the robustness of different voter topologies in the presence of transient and permanent faults. A fault masking ratio is used in a switch-level analysis to quantify the voter robustness. The results are validated through electrical simulations. Since the voters have their robustness usually evaluated considering stuck-at faults, this is the first work that evaluates this amount of voter topologies for transient and permanent faults at transistor-level. The results confirm that the high robustness topologies to stuck-at faults continue to present excellent results, but are not completely tolerant when evaluated at transistor-level.