Using FPGA self-produced transients to emulate SETs for SER estimation

The application of an electrical pulse to emulate a Single Event Transient (SET) is a strategy adopted in the study of pulse broadening and quenching effects. This strategy is usually restricted to the combinational circuits due to the temporal masking effect of the clock used in sequential circuits. Emulation-based fault-injection approaches, which consider the SET in addition to the SEU (Single Event Upset), do not use electrical pulses to emulate the SETs. Despite all these restrictions, an emulation-based fault-injection approach for Soft-Error Rate (SER) estimation, running on the same device chosen as the final target, is suitable for real electrical pulses for SET emulation. As the SER has a statistical nature, the fault-injection method does not need to control when the SET occurs inside the clock cycle. Instead, it needs to guarantee that the SET may occur at any moment, without bias. On the other hand, once using the same device, the concern about electrical distortion is restricted to the fault-injection process itself. In this context, this work presents an analysis of the use of an FPGA self-produced transient pulse as an emulated SET for SER estimation. The results show that is feasible to adopt this approach in some particular cases, with advantages related to the estimation process speed.