Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC

This work is set in the context of fault tolerance and reliability of critical cyber-physical systems (CPS) based on state-of-art commercial off-the-shelf (COTS) SRAM-based FPGA devices and, in special, the all programmable system-on-chips (AP-SoC) that are a class of devices combining a general purpose processing system (PS) with custom programmable logic (PL). In SRAM-based FPGAs the Single Event Upsets (SEU) are unavoidable and may alter the contents of storage elements such as flip-flop and, of interest to this work, the configuration memory (CRAM). We analyze the case of Xilinx Zynq-7000, which is based on multi-core ARM processor that, ultimately, provides as one of its major communication interface the ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI). In this context, we analyze reliability of communication interfaces between the embedded processor and the programmable logic and the different hardware modules on each side. For this, we deal with both (1) the development of experimental procedures and tools for fault injection on SRAM-based FPGAs and (2) the development of bottom-up reliability models that would allow estimating system level reliability by aggregating individual reliability from the different hardware modules and communication interfaces obtained from those experimental procedures and tools. In this scenario, fault injection contributes with fine grain reliability evaluation of each component module.