Planar Junctionless Silicon-on-Insulator Transistor With Buried Metal Layer

In this letter, we propose a novel structure of an n-channel silicon-on-insulator junctionless transistor (SOI-JLT) with improved I
_ON
/I
_OFF
ratio and scalability. A buried metal layer (BML) of appropriate workfunction (φ
_BM
) is used to create a Schottky junction at the bottom of Si device layer, whereas the source-channel-drain path is junctionless and hence named the buried-metal-SOI-lateral JLT (BM-SOI-LJLT). The BML-induced bottom depletion layer combined with the depletion region due to top gate results in a perfect volume depletion in OFF state. A 2-D calibrated simulation has shown an I
_ON
/I
_OFF
ratio of ~10
⁸
in BM-SOI-LJLT compared to ~2 in the conventional SOI-JLT at φ
_BM
of 5.1 eV and a gate length of 20 nm. Furthermore, the lateral band-to-band tunneling parasitic leakage is significantlylower in the BM-SOI-LJLT and does not degrade its I
_ON
/I
_OFF
ratio. Furthermore, high vertical field due to the Schottky junction minimizes the lateral coupling between the source and drain field lines and thus improves the shortchannel-effect suppression and scalability of the proposed device.