A generic processing in memory cycle accurate simulator under hybrid memory cube architecture

PIM was one of the attempts created during the 1990s to try to mitigate the notorious memory wall problem, where computational elements are added close, or ideally, inside the memory devices. Nowadays, with the maturation of 3D integration technologies, a new landscape for novel PIM architectures can be explored. To exploit this new scenario, researchers rely on software simulators to navigate throughout the design evaluation space. Today, most of the works targeting PIM implement an in-house simulator to perform their experiments. However, this methodology might hurt the overall productivity, and it can also preclude replicability. In this paper, we show the development of a precise, modular and parametrized PIM simulation environment. Our simulator has been developed using the SystemC allowing native parallel simulation. We have implemented the latest HMC technical specifications, including all HMC instructions. The primary contribution of our work lies on developing a user-friendly interface to allow easy PIM architectures exploitation. To evaluate our system, we have implemented a PIM module that can perform vector operations with different operand sizes using the proposed set of tools.