Interconnects

This chapter discusses the hierarchy of interconnection in ball grid array (BGA). The combination of eutectic bumps and the organic (FR4)‐based manufacturing processes are sound in thermal hierarchy, and thus, become mass production technology. The chapter focuses on the introduction to Level 1 interconnection, and gap in FC‐PBGA interconnection, and Level 0.5 interconnection. It presents discussion on the changing dynamics in business for more Moore (MM) and more than Moore (MTM), as a result of new through silicon via (TSV) interconnection technology. The chapter also discusses the changing semiconductor business dynamics. It summarizes the metallization used in silicon and III‐V compound semiconductors for wirebond and flip chip interconnections. The chapter shows that aluminum pads only exist on silicon, Gold (Au) pads only exist on III‐V, and Copper (Cu) can exist on both silicon and III‐V compound semiconductor integrated circuits (IC).