An architecture for 32-bit energy-efficient wallace tree carry save adder

In this paper, a hybrid 1-bit full adder design is reported. The design is first implemented for 1 bit full adder and further it has been utilize to design a 32-bit adder. The circuit is implemented using Tanner EDA tools in 45-nm technology. Power and delay performance parameters are compared with an existing design of hybrid CMOS full adder. In comparison with the existing design, the present implementation is found to offer substantial improvements in area power and speed. This work also proposes a 32-bit energy-efficient Wallace tree carry save adder on 45 nm technology. The design of the adder is based on a 1-bit hybrid full adder. Compared to the existing carry save adders, the proposed Wallace tree carry save based adder offers shorter delay, consumes lesser power dissipation, which makes it more cost-efficient and suitable for real-time applications.