16-Bit GDI multiplier design for low power applications

Today, more and more, high speed mobile computational devices and equipments are being introduced in the market. These computational devices strain and drain the battery very quickly. Researchers are making efforts to find ways and means to conserve the battery power for longer period. The core key components in these computational devices are the Multipliers to support high speed computational intensive applications in real time. Thus it becomes more important to reduce power dissipation and area in these multiplier modules as they affect the performance of the device. Several VLSI design techniques have been attempted to optimize the power and area occupied by the multiplier module, but there are very few design techniques that gives the required extensibility both in terms of power and area. In this paper a high speed, reliable and efficient 16 bit multiplier VLSImodule design is presented using GDI (Gate Diffusion Input) technique, addressing both power consumption and area complexity. Further, comparative study results of the proposed design over the traditional CMOS design are also presented. Detailed design steps and comparative study using Cadence Virtuoso simulation tool at 180nm CMOS technology is discussed. The simulation results presented show reduction in both power and area of the proposed design at 1.8Vsupply voltage.