Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder

Exploiting the tradeoff between accuracy and hardware cost has a tremendous potential to improve the efficiency of integrated systems. Using this concept, numerous approximate adders have been proposed in the last ten years. Although conceptually different, all previous architectures have been obtained with an ad hoc and nonsystematic methodology. Instead, this brief generalizes and systematically optimizes an architectural template for approximate adders. The outcome, called optimized lower part constant-OR adder (LOCA), outperforms previous approaches in terms of accuracy and hardware cost. For example, an 8-bit approximate adder implemented with our new approach improves the mean squared error by 58.5%, while simultaneously reducing the cost by 7.2% with respect to the previously reported best architecture.