Delay Monitor Circuit and Delay Change Measurement Due to SEU in SRAM-Based FPGA

This paper presents a monitor circuit designed for the detection of extra combinational delays in a high-frequency SRAM-based field-programmable gate array (FPGA). Since in most of the SRAM-based FPGAs, more than 90% of the configuration bits control the routing resources, systems designed on FPGA are particularly vulnerable to interconnection delay changes (DCs) caused by single-event upset (SEU) affecting the configuration memory. The proposed monitor is part of a mitigation technique dedicated to protect the circuit routing delay integrity while the system is being exposed to SEUs generated by radiation. Experimental results show that the probability of DC occurrence can increase when the number of DCs affecting a node increases. Indeed, this increase depends on the configurable interconnection network and design placement in FPGA. Delay measurements using the proposed monitor revealed the existence of single DCs ranging from 29 to 151 ps. Also, cumulative DCs in the range of 279-309 ps being the results of an extra interconnection network added by SEUs have been detected. Measured delay values are in good agreement with those observed experimentally under proton radiation and also circuit-level simulations and emulations.