Developing a standardized method for measuring and quantifying dynamic on-state resistance via a survey of low voltage GaN HEMTs

Designing and optimizing high frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistance, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) transistors was plagued by detrimental dynamic on-state resistance effects. This non-linear, second-order phenomenon for GaN devices is characterized by an increase in on-state resistance with increasing voltage and temperature stress. While device manufacturers have made significant improvements compared to early generation devices, experimental evidence for a survey of commercial GaN transistors highlights that significant increase in on-state resistance with voltage and temperature stress still exists. This new method for measuring dynamic on-state resistance has the promise to shed new light on the dynamic on-state resistance limitations of GaN devices due to the independent control of drain current, voltage stress, pulse-width for device conduction time, and package temperature. Based on a survey of low voltage GaN transistors, two metrics are proposed not only to quantify the dynamic on-state resistance performance of a specific device, but also to facilitate a fair comparison between different GaN device technologies.