Near time optimal recovery in a digitally current mode controlled buck converter driving a CPL

Stability of a distributed power architecture (DPA) still remains a major concern, even though individual stand-alone DC-DC converters are designed with sufficient (small-signal) stability margins. In such architectures, a tightly regulated point-of-load (PoL) converter resembles a constant power load (CPL) which introduces a negative-impedance effect to the source converter. This effect may introduce limit cycle oscillation (LCO) and may eventually destabilize the overall DPA. In this paper, a source buck converter is considered under digital current-mode control (DCMC) with a proportional-integral (PI) voltage controller, which is driving a CPL buck converter. During a power step-transient in the CPL, stable controller gain ranges under DCMC are computed for the source converter for individual operating conditions. Thereafter, a phase-plane based geometric framework is proposed to compute the optimal proportional gain for the source converter to achieve near time optimal recovery. A hardware prototype is made with 50 W nominal power ratings for individual converters. Analytical predictions and improved performance are validated experimentally.